It is well-known that adding a dither signal to a desired signal prior to quantization can render the quantizer error independent of the desired signal. Classic examples of this work deal with the quantization of analog signals. Advances in digital signal processing speed and large scale integration have led to the development of all-digital receiver systems, direct digital frequency synthesizers and direct digital arbitrary waveform synthesizers. In all these applications, because finite word-length effects are a major factor in system complexity, they may ultimately determine whether it is efficient to digitally implement a system with a particular set of specifications. Earlier work has presented a technique for reducing the complexity of digital oscillators through phase dithering with the claim of increased frequency resolution. Recent research has suggested mitigation of finite-word-length effects in the synthesis of oversampled sinusolds through noise shaping. It would be useful if the analysis techniques used for quantization of analog signals can be applied to overcome finite-word-length effects in digital systems. It would also be advantageous if appropriate dither signals can be used to reduce word lengths in digital sinusold synthesis without suffering the normal penalties in spurious signal performance.
Conventional methods of digital sinusoid generation, e.g., FIG. 1, result in spurious harmonics (spurs) which are caused by finite word-length representations of both amplitude and phase samples. Because both the phase and amplitude samples are periodic sequences, their finite word-length representations contain periodic error sequences, which cause spurs. The spur signal levels are approximately 6 dB per bit of representation below the desired sinusoidal signal.
A search of the most relevant prior art resulted in the following U.S. Patents:
______________________________________ 4,652,832 Jasper 4,926,130 Weaver 4,994,803 Blackham 5,014,231 Reinhardt et al 5,017,880 Dugan et al 5,029,120 Brodeur et al 5,036,294 McCaslin 5,073,869 Bjerede 5,091,921 Minami 5,108,182 Murphy 5,121,409 Goss 5,128,623 Gilmore 5,131,750 Gravel et al 5,151,661 Caldwell et al 5,162,746 Ghoshal 5,166,629 Watkins et al 5,184,093 Itoh et al ______________________________________
Of the foregoing patents, the following appear to be the most pertinent:
U.S. Pat. No. 5,073,869 to Bjerede is directed to suppression of spurious frequency components in a direct digital frequency synthesizer. The improved direct digital frequency synthesizer has a coarse 48/fine accumulator 40 and a non-linear digital-to-analog converter 42. The accumulator suppresses the generation of spurious frequency components in the analog waveform output of the synthesizer by randomly dithering the phase at which the coarse component accumulator 48 is incremented by the phase accumulator 40. The sample-and-hold circuit 44 mitigates spurs induced by glitches from the digital to analog converter by sampling the analog signal 56 at times when the glitches are not present.
U.S. Pat. No. 4,994,803 to Blackham is directed to a random number dither circuit for digital to analog output signal linearity. Distortion is reduced in a linear circuit by adding a random digital number to the input and subtracting the equivalent random analog number from the output. A digital number from random number generator 14 is summed with the input digital number and is converted to an analog number by DAC 18. The summed input and random number is converted to an analog signal by DAC 24 and the output of 18S is subtracted in summer 22 to provide the distortion-free output.
U.S. Pat. No. 5,162,746 to Ghoshal is directed to a circuit for attenuating phase jitter in a clock signal that includes a dithering circuit, a phase locked loop, and a digitally controlled oscillator. The dithering circuit modulates the digitally controlled oscillator to improve rejection behavior when the incoming clock frequency is substantially the same as the divided down oscillator signal.
U.S. Pat. No. 5,108,182 to Murphy is directed to a digital path length control for a ring laser gyro comprising a dither counter, a dither DAC, a control counter, a control DAC, and a piezoelectric transducer path length control driven by two DAC's. The dither modulates the operating conditions to center rather than at either extreme of the system error.
U.S. Pat. No. 5,036,294 McCaslin is directed to a phase locked loop having low frequency jitter compensation. An output clock that is in-phase with a reference clock utilizes a dither circuit to control the switching of the phase locked loop. A switch capacitor phase locked loop 10 has a dither portion 16 that translates the low frequency intrinsic jitter to a higher frequency jitter where it is more tolerated.
None of the aforementioned prior art discloses a method and apparatus for exponentially decreasing the complexity of numerically-controlled oscillators and direct digital frequency synthesis with only a small increase in system noise.